Through its LEAST Center, ND leads the way in low-power microelectronics
By Prof. Thomas Fuja, Chair, Department of Electrical Engineering. Originally published in the September 2014 issue of "Electrical Engineering at the University of Notre Dame" newsletter.
The largest research award ever made to Notre Dame is now almost two years old – and its results could reshape the microelectronics industry.
It was in January 2013 that it was announced that Notre Dame had been selected to lead one of six new university-based microelectronics research centers co-sponsored by the industry consortium Semiconductor Research Corporation (SRC) and the U.S. Defense Advanced Research Projects Agency (DARPA). The Notre Dame initiative, called the Low Energy Systems Technology (LEAST) center, was established as part of the five-year, $194 million STARnet program, designed to support the continued growth and leadership of the U.S. semiconductor industry.
The LEAST Center, led by Notre Dame Professor of Electrical Engineering Alan Seabaugh, receives funding of approximately $6 million per year. The Center’s 26 faculty members work at Notre Dame and ten partner universities: Carnegie Mellon, Georgia Tech, Illinois Institute of Technology, Penn State, Purdue, UC Berkeley, UC San Diego, UC Santa Barbara, UT Austin, and UT Dallas. As the lead institution, Notre Dame is home to more researchers than any other university in the consortium and also receives the largest share of the external funding.
The focus of LEAST is the development of new electronic materials, devices, and architectures that enable ultra-low power operations. The motivation behind LEAST is that the “workhorse” digital switching technology for the last 40 years – silicon-based CMOS – is fast approaching a point where it cannot be scaled any smaller due to limits on heat dissipation. Therefore, to extend Moore’s Law – and to continue making electronic devices that are smaller, cheaper, faster, and more pervasive than what came before – requires developing a new switching technology based on (potentially) different material systems.
From a technical perspective, part of the impetus for LEAST’s research agenda was the work done on tunneling field-effect transistors (TFETs) in an earlier Notre Dame research center. The Midwest Institute for Nanoelectronics Discovery (MIND) was established at Notre Dame in 2008 with funding from the SRC and the National Institute of Standards and Technology (NIST). Like LEAST, its predecessor MIND addressed “post-CMOS” technologies, and TFET research was one of the pillars of MIND’s research agenda. TFETs use a different phenomenon to effect switching than conventional MOSFET technology – quantum tunneling through a barrier rather than thermionic emission over a barrier – and so TFETs can exhibit a steep “subthreshold swing” that enables operation at less than 0.4 V, thus reducing power consumption dramatically.
Ultimately, the TFET research carried out as part of MIND was a victim of its own success. The industry partners funding MIND decided that TFETs were so promising that they would take them “in house” – i.e., continue their development internally, rather than as part of a shared and relatively-open research collaboration.
However, the MIND research also indicated that the ultra-low voltages and steep transitions associated with TFETs were not limited to TFETs, so the proposal that ultimately resulted in the LEAST award set forth a multi-pronged research agenda dedicated to other technologies exhibiting steep transitions between their on and off states – i.e., less than 60 mV/decade of current at room temperature.
“Anyone with a laptop feels the heat it generates,” said LEAST director Alan Seabaugh. “In data centers, this heat requires a costly cooling system. Heat prevents us from packing more transistors onto a computer chip. The mission of LEAST is to discover devices which will run cooler and pack tighter. This will change the rules limiting how many transistors we can put on a chip and how fast we can operate them.”
There are four technical “themes” that LEAST uses to organize its research agenda:
1. Materials, interfaces, and surfaces – with sub-themes that include oxide-based and nitride-based materials as well as two-dimensional crystals.
2. Quantum-engineered steep transistors – aimed at understanding and demonstrating steep-slope tunneling devices in 2D graphene and dichalcogenide crystals, III-Nitrides, and complex oxides.
3. Transduction components – exploring transduction mechanisms beyond tunneling to further lower subthreshold swing and add new functionality to steep devices.
4. Benchmarks, circuits, and architectures – providing benchmarking activities for the Center and exploring applications for steep technologies, including low-power digital logic, low-power analog, high-frequency mixed signal, security, non-von-Neumann machines, and non-Boolean computing.
In the year and a half since LEAST took flight, both the quantity and the quality of the sponsored research has been staggering. In just 17 months, LEAST researchers have already submitted over 300 technical papers – a rate of about four per week. Moreover, the LEAST research is “spinning off” ideas that are launching other NSF and Department of Defense proposals, including a recent successful NSF proposal to develop two-dimensional memory technology. LEAST faculty members continue to be recognized for their research success.
Undergraduates are also playing a substantial role in LEAST. One of Notre Dame’s EE undergrads won a STARnet summer internship to work at UT Dallas in the summer of 2014, while another four undergraduates received Undergraduate Research Fellowships from the Notre Dame Center for Nano Science and Technology.
In August 2014, LEAST held its second review, bringing to campus researchers from its industrial partners at Applied Materials, Intel, IBM, Texas Instruments, GLOBALFOUNDRIES, Micron, Raytheon, and United Technologies. The review featured both talks by faculty on the latest transistor demonstrations and a large poster session with more than 50 posters by graduate students and post docs. Fundamental theory for four new transistors was developed this year and presented at the meeting, and circuit simulation models have been developed for the TFET and another ND-invented transistor, the SymFET (symmetric graphene TFET). One of these TFET models was implemented on Android and iPhone platforms and will be available soon, allowing anyone to explore TFET circuit designs on the application AIMSPICE.
The development of new device and circuit models have, in turn, enabled new directions for research in computing, pattern recognition, imaging, energy harvesting, sensor networks, and security. Five patents from LEAST-sponsored research are in process.
Anyone interested in learning more about Notre Dame’s LEAST Center is invited to visit its home page at http://least.nd.edu/.